High PSR voltage regulator architecture for GDDR6 application

ABSTRACT

The embodiments described herein provide for methods and systems for removing power supply induced jitter from a Phase Lock Loop to provide a Power Supply Induced jitter-free clock signal to a system-on-a-chip and GDDR6 DRAM interface. In operation, a circuit reduces a DC offset between a reference voltage and a voltage regulator output to identify low frequency noise on the voltage regulator output to apply as negative feedback to reduce the low frequency noise on the voltage regulator output. The bandwidth of the circuit is increased to detect high frequency noise, which is applied as negative feedback on the voltage regulator output. Very high frequency noise is then detected and applied as negative feedback to the voltage regulator output. The circuit outputs a regulated output equal to the reference voltage and immune to the low, high, and very high frequency noise of power delivery network supply to the regulator.

TECHNICAL FIELD

The present invention relates generally to the field of voltageregulation in high-speed memory interface systems. More specifically,the present invention relates generally to reduction of power supplyinduced jitter in a high-speed memory interface system.

BACKGROUND

Emerging technologies like artificial intelligence, machine learning,and high-speed graphics need a high-speed memory interface tocommunicate with high bandwidth memory, such as dynamic random accessmemory (DRAM), for use in graphics cards, game consoles, andhigh-performance computing, such as graphics double data rate type sixsynchronous dynamic random access memory (GDDR6 DRAM), which has anoperating speed of 24 Gbps. In a system-on-a-chip (SOC) interfacing witha GDDR6 DRAM, a write mode allows the SOC to transmit parallel data andan SOC clock to the DRAM, and the DRAM samples the parallel data signalsusing the SOC clock to obtain a set of data samples to be stored in theDRAM. In a read mode, the DRAM transmits parallel data back to the SOC,and the SOC reuses the SOC clock to sample the parallel data transmittedfrom the DRAM. In such a device, the DRAM may also transmit an ErrorDetection Code (EDC) signal, which the SOC uses to align the SOC clockwith the parallel data received from the DRAM. The system may include aPhase Lock Loop (PLL) used to generate the clock for the systemconnected to a same power supply as the SOC and GDDR6 DRAM.

In some high-performance memory systems, like GDDR6, there can beaccumulation jitter in the PLL due to a delay of up to 2.5 ns betweenthe clock edge at which the DRAM transmits parallel data to the SOC andthe clock edge at which SOC actually receives the sampled DRAM data. Theaccumulation jitter includes random noise dominated by device-inducednoise and deterministic noise dominated by noise on the power supply.The deterministic noise may also include high levels of SimultaneousSwitching Noise (SSN) on the power supply caused by the use of aparallel interface DRAM system (e.g., such as GDDR6), and dominates theaccumulation jitter. The accumulation jitter results in a reduction ofthe clock read trimming margin for the SOC receiver, increasing thelikelihood of a failed read operation in such high-speed systems.

To operate at full capacity, GDDR6 systems require minimization of thedeterministic noise of the accumulation jitter, such as reducing powersupply induced jitter (PSIJ) in the PLL, so that the PLL generates aclock with minimal delay. One conventional method of improving PSIJincludes providing the PLL with a dedicated power supply, however, thepackage coupling and inside chip coupling between supplies can cause theactual power supply reaching the PLL to be very noisy. Additionalmethods include using an on-chip regulator with high Power SupplyRejection (PSR) to filter out power supply noise before it reaches thePLL. Two such conventional on-chip regulators known in the art involvetypes of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)drivers: an N-type MOSFET (NMOS) power driver-based, on-chip regulatorarchitecture 100 a, shown in FIG. 1A; and a P-type MOSFET (PMOS) powerdriver-based, on-chip regulator architecture 100 b, shown in FIG. 1B.

The conventional NMOS power driver-based regulator 100 a, shown in FIG.1A, includes a comparator 102 a and an NMOS power driver 104 a whichprovides the regulator output to a PLL 106 a and to an input of thecomparator as negative feedback. This architecture offers the benefitsof low output impedance, improved load current regulation, and good PSR.However, in such an architecture, the power supply voltage VDDQ isrequired to be greater than the sum of the regulated output voltage VREGand the NMOS power driver 104 a threshold voltage (Vth). In a GDDR6system during a 5 nm T7G process, the power supply voltage VDDQ of GDDR6can be as low as 1.21V, the regulated output voltage VREG can be as highas 0.88V, and the Vth can be as high as 0.5V; the power supply voltageVDDQ is insufficient to power the GDDR6 process, as 0.88V+0.5V=1.38V,which is greater than the low end of power supply voltage VDDQ at 1.21V.Thus, the NMOS power driver-based regulator 100 a cannot be used forGDDR6 applications because of the architectures power supplyrequirements.

The conventional PMOS power driver-based regulator 100 b, depicted inbackground art FIG. 1B, includes a comparator 102 b and a PMOS powerdriver 104 b. Similar to the NMOS power driver based solution, the PMOSpower driver based solution provides the regulator output to both a PLL106 b and an input of the comparator as negative feedback. Unlike theNMOS-based architecture 100 a described with reference to FIG. 1A, thePMOS power driver-based regulator architecture 100 b does not sufferfrom the same power supply limitations and can operate for the powersupply voltage VDDQ power supply less than regulated output voltage VREGplus PMOS power driver 104 b threshold voltage (Vth). The PMOSarchitecture also provides good PSR for low frequency power supplynoise. However, the PSR of this regulator architecture is limited by thebandwidth of the comparator 102 b. GDDR6 requires 200 MHz-300 MHz ofbandwidth. Increasing the bandwidth of comparator 102 b can compromisethe stability of the negative feedback loop, resulting in limitedbandwidth and poor PSR for high frequency power supply noise. Thus, thePMOS power driver-based regulator 100 b cannot be used for GDDR6applications because the bandwidth limitations cannot effectively filterthe high frequency power supply noise.

SUMMARY

Disclosed herein are systems and methods for voltage regulation designedto address the above-noted shortcomings of conventional voltageregulation of power supply input above-noted shortcomings ofconventional voltage regulation of power supply input to a PLL for clockgeneration in high-speed memory systems, and may provide additional oralternative benefits as well. There is a desire for new methods and/orhardware components that provide good PSR to minimize PSIJ on the powersupply of the PLL to enable the PLL to generate a clock with minimalaccumulated deterministic jitter. The embodiments described hereinprovide for a voltage regulator architecture with high PSR capable ofreducing the PSIJ of the PLL power supply across a large bandwidth offrequencies. The embodiments described herein further provide for avoltage regulator architecture capable of meeting the deterministicjitter target for maintaining the timing budget for a 24 Gbps GDDR6 PLLinterface.

In an embodiment, a voltage regulator circuit comprises a first feedbackcircuit loop configured to receive a reference voltage and a voltageregulator output; detect a low frequency noise from a regulator powersupply on the voltage regulator output using the reference voltage andthe voltage regulator output; and apply the low frequency noise as a lowfrequency negative feedback to the voltage regulator output, therebyreducing the low frequency noise on the voltage regulator output. Thecircuit further comprises a second feedback circuit loop having acomparatively higher bandwidth than the first feedback circuit loop, andconfigured to: increase bandwidth of the voltage regulator circuit, andreduce a high frequency noise from the regulator power supply. Thecircuit further comprises a third feedback circuit loop configured to:detect a very high frequency noise from the regulator power supply onthe voltage regulator output; apply the very high frequency noise as avery high frequency negative feedback to the voltage regulator output,thereby reducing the very high frequency noise on the voltage regulatoroutput; and output a regulated output equal to the reference voltage andimmune to the low frequency noise, the high frequency noise, and thevery high frequency noise from the regulator power supply.

In another embodiment, a method for voltage regulation in a regulatorcircuit, the method comprising receiving, by a first feedback circuitloop, a reference voltage and a voltage regulator output; detecting, bythe first feedback circuit loop, a low frequency noise from a regulatorpower supply on the voltage regulator output using the reference voltageand the voltage regulator output; applying, by the first feedbackcircuit loop, the low frequency noise as negative feedback to thevoltage regulator output, thereby reducing the low frequency noise onthe voltage regulator output; increasing, by a second feedback circuitloop, bandwidth of the circuit, the second feedback circuit loop havinga comparatively higher bandwidth than the first feedback circuit loop,reducing, by the second feedback circuit loop, high frequency noise onthe voltage regulator output; detecting, by a third feedback circuitloop, very high frequency noise from the regulator power supply on thevoltage regulator output; applying, by the third feedback circuit loop,the very high frequency noise as negative feedback to the voltageregulator output, thereby reducing the very high frequency noise on thevoltage regulator output; and outputting, by the third feedback circuitloop, a regulated output equal to the reference voltage and immune tothe low frequency noise, the high frequency noise, and the very highfrequency noise from the regulator power supply.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure can be better understood by referring to thefollowing figures. The components in the figures are not necessarily toscale, emphasis instead being placed upon illustrating the principles ofthe disclosure. In the figures, reference numerals designatecorresponding parts throughout the different views.

FIGS. 1A-1B are block diagrams illustrating conventional voltageregulator architectures.

FIGS. 2A-2C are schematics illustrating a same voltage regulatorarchitecture highlighting different feedback circuit loops, according toan embodiment.

FIG. 3 is a flow chart detailing a circuit-implemented method forvoltage regulation, according to an embodiment.

FIG. 4A shows a clock output of a PLL using a conventional voltageregulator architecture.

FIG. 4B shows a clock output of a PLL using a voltage regulatorarchitecture, according to an embodiment of the proposed regulatorarchitecture disclosed herein.

DETAILED DESCRIPTION

Reference will now be made to the exemplary embodiments illustrated inthe drawings, and specific language will be used here to describe thesame. It will nevertheless be understood that no limitation of the scopeof the invention is thereby intended. Alterations and furthermodifications of the inventive features illustrated here, and additionalapplications of the principles of the inventions as illustrated here,which would occur to a person skilled in the relevant art and havingpossession of this disclosure, are to be considered within the scope ofthe invention.

The embodiments herein provide an improved system and method for voltageregulation of a power supply by combining several negative feedbackcircuit loops, also called “feedback loops,” targeted towards orotherwise designed for different frequencies and bandwidths to reducethe deterministic accumulation jitter of the PLL in a 24 Gbps GDDR6 PLL.The voltage regulator includes a low frequency feedback loop directedtowards reducing a direct current (DC) offset between an output voltageand an input reference voltage. The low frequency feedback loop has abandwidth (e.g., 20 MHz bandwidth) sufficient to detect and reduce noiseat low frequency (e.g., frequencies less than 20 MHz).

The voltage regulator architecture also includes a high frequencyfeedback loop directed towards increasing the bandwidth of the circuitby having a comparatively higher bandwidth (e.g., 200 MHz bandwidth)than the low frequency feedback loop, and detects and reduces noise athigh frequency (e.g., frequencies from 20 MHz to 100 MHz).

The voltage regulator architecture further includes a very highfrequency detection and correction feedback loop directed towardsproviding improvement in high frequency PSR. The very high frequencyfeedback loop has a bandwidth that is comparatively higher than thebandwidth of the high frequency feedback loop, is centered at a resonantfrequency of a power supply to the circuit (e.g., centered at or around167 MHz), and is sufficient to detect and reduce noise at very highfrequency (e.g., frequencies from 100 MHz to 300 MHz). The feedbackloops in the voltage regulator architecture are linked together andoperate as a single circuit concurrently to beneficially filter PSIJ andreduce low, high, and very high frequency noise from the power supplysignal across a large bandwidth of frequencies for input to the PLL.

FIGS. 2A-2C illustrate a high PSR voltage regulator architectureschematic as a circuit 200, according to an illustrative embodiment.Circuit 200 includes a first feedback loop 214, that can receive areference voltage as a first input signal and a voltage regulator output(an output of the regulator circuit) as a second input signal, detect alow frequency noise on the second input signal using the first inputsignal and the second input signal, and apply the low frequency noise asa low frequency negative feedback to the second input signal, therebyreducing the low frequency noise on the output of the regulator.

Circuit 200 further includes a second feedback circuit loop 216, whichhas a comparatively higher bandwidth than first feedback loop 214, andcan increase bandwidth of the circuit 200. First feedback loop 214 candetect and reduce a high frequency noise on the regulator output byapplying high frequency noise as high frequency negative feedback.Circuit 200 includes a third feedback circuit loop 218 that can detect avery high frequency noise on the regulator output, and apply the veryhigh frequency noise as very high frequency negative feedback to reducethe very high frequency noise on the regulator output. As a result ofthe functions of the feedback loops 214-218 of the circuit 200, theregulator output signal is unaffected by the low frequency noise, thehigh frequency noise, and the very high frequency noise produced by theregulator power supply.

Each of FIGS. 2A, 2B, and 2C depicts the circuit 200 and encirclesfeedback loops 214-218 respectively. Circuit 200 uses feedback loops214-218 in conjunction with a PMOS power driver 208 that receives apower supply voltage VDDQ (sometimes referred to as regulator powersupply voltage) from a power delivery network (not pictured) and outputsa regulated voltage VREG (sometimes referred to as regulated outputvoltage or regulator output voltage). PMOS power driver 208 receivespower supply voltage VDDQ as a source input and negative feedbackgenerated by feedback loops 214-218 as a gate input, and outputsregulated voltage VREG at a drain output, which is a noise andamplitude-reduced version of power supply voltage VDDQ. When received atthe gate input of PMOS power driver 208, the negative feedback fromfeedback loops 214-218 alter a gate-source voltage of PMOS power driver208. The gate-source voltage determines the amount (e.g., amplitude andfrequency) of power supply voltage VDDQ allowed to pass from source todrain in PMOS power driver 208, effectively filtering noise from powersupply voltage VDDQ to generate a regulated voltage, regulator outputVREG.

Circuit 200 includes a plurality of MOSFET devices (e.g., PMOStransistors and NMOS transistors) to implement voltage regulationthrough negative feedback. This is achieved across feedback loops214-218 by using multiple PMOS and NMOS transistors, which act similarto voltage-controlled resistors. In FIGS. 2A-2C, a solid line betweensource and drain on any of the PMOS or NMOS transistors indicate that itis a depletion-type MOSFET (e.g., normally “on”). When a bias voltage isapplied to a gate of any of the MOSFET transistors, the transistorchannel begins to pinch-off, meaning transconductance of the MOSFET ischanged and an alternating current (AC) power supply signal passingthrough is altered. Because an output signal (e.g., bias signal) of aMOSFET is an inverted and attenuated version of an input signal, whenthe output signal is connected to the input signal, negative feedbackoccurs, meaning the output signal cancels out some of the input signal.The negative feedback over time results in a consistent output signalmaintained at a specific level. Since noise is prevalent in high-speedmemory systems, PMOS transistors, due to their high noise immunity andcontrollability with low gate voltages, are ideal for use in circuitrequiring negative feedback amplifiers, therefore best used as powerdrivers in feedback loops 214-218. NMOS transistors are superior forapplications involving high-speed switching, and therefore are used inthe very high frequency detection by third feedback loop 218.

FIG. 2A illustrates a first feedback loop 214 of circuit 200, accordingto the embodiment. The first feedback loop 214 may be configured toapply a low frequency noise as a negative feedback to a second inputsignal, represented as output of the regulator VREG, thereby reducingthe low frequency noise on the output of the regulator. First feedbackloop 214 can include a comparator 202, a net (Net 1), a PMOS device 210,and a capacitor (C1). In some embodiments, first feedback loop 214maintains a bandwidth of less than 20 MHz and a DC gain of over 40 dB,and is bandwidth-limited by comparator 202. In some embodiments, thefirst feedback loop 214 may be configured to receive a first inputsignal at a first input 204 and the second input signal at a secondinput 206. Comparator 202 can receive the first input signal at firstinput 204 and the second signal at second input 206.

The first input signal received at first input 204 is used as areference voltage VREF, (sometimes referred to as a reference signal).The reference voltage VREF may be set by an SOC (not pictured) coupledto the voltage regulator or another voltage supply source. The secondsignal received at second input 206 may be at least a portion ofregulator output VREG outputted by PMOS power driver 208, whichcomparator 202 uses as negative feedback to reduce a DC offset betweenthe regulator output VREG and the reference voltage VREF. In operation,comparator 202 effectively identifies differences (representing noiseoccurring at frequencies within the bandwidth) between regulator outputVREG and reference voltage VREF, and can output a signal comprisingnoise as a DC bias voltage to a PMOS device, such as PMOS device 210,via Net 1. In some embodiments, the first feedback loop 214 may beconfigured to apply the low frequency noise (e.g., the DC bias voltage)as negative feedback by inputting the low frequency noise to a gate of aPMOS device, for example, PMOS device 210.

Net 1 is a circuit net providing a conductive path between comparator202 and the gate of PMOS device 210. The gate of PMOS device 210receives the DC bias voltage, thereby altering a gate-source voltage ofPMOS device 210. PMOS device 210 receives a source input signal, whichin some embodiments is at least a portion of regulator output VREG. TheDC bias voltage generated by comparator 202 allows a portion ofregulator output VREG free of the DC bias noise through PMOS device 210.

In some embodiments, the bandwidth of the first feedback loop 214 isless than 20 MHz and a DC gain of the first feedback loop 214 is greaterthan 40 dB. Because the bandwidth of first feedback loop 214 is lessthan 20 MHz, first feedback loop 214 can effectively remove lowfrequency noise in regulator output VREG at PMOS device 210 in thismanner. Capacitor C1 reduces high frequency switching noise on theregulator output VREG.

FIG. 2B illustrates second feedback loop 216 of circuit 200, accordingto an embodiment. Second feedback loop 216 may include one or moredevices and has a comparatively higher bandwidth than first feedbackloop 214; the comparatively higher bandwidth of second feedback loop 216increases the overall effective bandwidth of circuit 200 for the purposeof reducing high frequency noise. Second feedback loop 216 includes PMOSdevice 210, a resistor R1, nets (Net 2, Net 3), NMOS device 220, andPMOS power driver 208.

By having a comparatively higher bandwidth than first feedback loop 214,second feedback loop 216 can increase the bandwidth of the circuit 200to enable reduction of high frequency noise. In some embodiments,bandwidth of the second feedback circuit loop 216 is 200 MHz. In somecases the second feedback loop 216 may reduce high frequency noise at oraround 100 MHz, though the bandwidth of the second feedback loop 216 maybe effectively higher (e.g., 200 MHz) than the frequency of the noiseintended for reduction (e.g., 100 MHz). In some embodiments, secondfeedback loop 216 can receive a bias voltage component from the thirdfeedback loop 218 as negative feedback, the bias voltage sufficient toreduce the high frequency noise on the regulator output VREG. In theembodiments described herein, second feedback loop 216 reduces highfrequency noise on regulator output VREG by using PMOS power driver 208,PMOS device 210, and NMOS device 220.

Devices of second feedback loop 216 (e.g., PMOS power driver 208, PMOSdevice 210, and NMOS device 220) may set a DC gain, which typically hasan inverse relationship with bandwidth. The DC gain is set low enough toachieve a sufficiently high bandwidth for second feedback loop 216 (andthus, circuit 200). High bandwidth is necessary in order for circuit 200to correct high frequency noise of the second input signal and regulatoroutput VREG. The bandwidth increase requires some DC bias current, whichPMOS device 210 provides to second feedback loop 216 and maintains at acorrect voltage level by biasing resistor R1. Second feedback loop 216may be configured to use a limited DC bias current such that overallpower consumption of the regulator is sufficiently small to ensure amajority of current from power supply voltage VDDQ is output to the PLL,and not consumed by circuit 200.

Although not directly in the current path of second feedback loop 216,NMOS device 222, resistors R2, R4, and a capacitor C4 may contribute toother functions of second feedback loop 216. For example, resistor R2and NMOS device 222 generate a DC bias voltage component for a gateinput of NMOS device 220 from input power supply voltage VDDQ, andresistor R4 and capacitor C4 further increase the bandwidth of secondfeedback loop 216. The DC bias voltage applied to the gate input of NMOSdevice 220 has two components, the first of which is generated byresistor R2 and NMOS device 222. The first DC bias voltage component isa slightly filtered version of power supply voltage VDDQ, which, whenreceived by a portion of circuit 200 having a bandwidth of 200 MHz(e.g., second feedback loop 216), has noise at frequencies at an upperlimit of the bandwidth (e.g., at or around 200 MHz). Thus, the firstcomponent of the DC bias voltage (e.g., the DC bias voltage of secondfeedback loop 216) is applied as negative feedback sufficient toeffectively remove high frequency noise.

From PMOS device 210, the portion of regulator output VREG free of lowfrequency noise passes to a source input of NMOS device 220 via Net 2,which is a circuit net providing a conductive path between a drainoutput of PMOS device 210 and the source input ofNMOS device 220. The DCbias voltage input to the gate of NMOS device 220 determined by resistorR2 and NMOS device 222 determines the portion of regulator output VREGallowed to pass through NMOS device 220. As the bandwidth of secondfeedback loop 216 is directed towards frequencies greater than 20 MHz,only the noise at those frequencies will be filtered out of regulatoroutput VREG at NMOS device 220. From NMOS device 220, the portion ofregulator output VREG now clear of high frequency noise passes to a gateof PMOS power driver 208 as a DC bias voltage via Net 3, which is acircuit net providing a conductive path between a drain output of NMOSdevice 220 and a gate of PMOS power driver 208. Similar to the result offirst feedback loop 214, the result of the implementation of secondfeedback loop 216 is essentially regulator output VREG free of lowfrequency noise and high frequency noise.

FIG. 2C illustrates a third feedback loop 218, according to anembodiment. Third feedback loop 218 can detect a very high frequencynoise on regulator output VREG. Third feedback loop 218 can furtherapply the very high frequency noise as negative feedback to regulatoroutput VREG, thereby reducing the very high frequency noise on regulatoroutput VREG.

In some embodiments, the very high frequency noise detected by the thirdfeedback circuit loop is within a predetermined threshold of a powerdelivery network resonant frequency. Third feedback loop 218 may be aband-pass filter with a band frequency centered on the power deliverynetwork resonant frequency. The effective bandwidth of third feedbackloop 218 may be greater than the power delivery network resonantfrequency.

In circuit 200, third feedback loop 218 operates as a very highfrequency noise detection and correction circuit loop, in which noise atfrequencies surrounding a resonant frequency of the power deliverynetwork providing power supply voltage VDDQ. The configuration of thirdfeedback loop 218 achieves the goal of filtering out the very highfrequency noise often present in power supply signals and compensatesfor the limited gain of second feedback loop 216 at high or very highfrequencies. The three feedback loops 214-218 cover the range offrequencies (low, high, and very high) necessary to achieve a noise-free(or noise-diminished) regulated power supply to the PLL.

Third feedback loop 218 includes coupling capacitor C2, capacitor C3,nets (Net 3, Net 4, Net 5, Net 6), NMOS device 220, NMOS device 226, andPMOS power driver 208. Using these components, third feedback loop 218generates a second component of the DC bias voltage. Although notdirectly in the current path of third feedback loop 218, NMOS device224, resistor R3, NMOS device 228, and PMOS devices 230-238 contributeto other functions of third feedback loop 218. For example, NMOS device224 sets a DC bias voltage for a gate of NMOS device 226; resistor R3works in conjunction with capacitor C3 to perform detection of very highfrequency noise on regulator output VREG; NMOS device 228 providesamplification of the detected high frequency noise of regulator outputVREG; and PMOS Devices 230-238 provide DC bias current (I_(BIAS) in FIG.2C) to multiple devices in circuit 200 using a connecting net (Net 7).Net 7 is a circuit net connecting PMOS devices 230-238 to a currentdevice 240 generating I_(BIAS). In some embodiments, current device 240is a voltage-controlled current source or a current-controlled currentsource.

In some embodiments, third feedback loop 218 applies the very highfrequency noise as the very high frequency negative feedback byamplifying the very high frequency noise, thereby producing amplifiedvery high frequency noise. A gate of NMOS device 220 may receive theamplified very high frequency noise as the negative feedback. A sourceof NMOS device 220 may receive at least a fraction of the regulatoroutput VREG. Third feedback loop 218 may reduce the very high frequencynoise on the regulator output VREG.

In circuit 200, third feedback loop 218 receives regulator output VREGat capacitor C3, which works in conjunction with resistor R3 to detectvery high frequency noise. After detection, capacitor C3 outputs thedetected noise to a gate of NMOS device 226 via Net 4. NMOS device 226works with NMOS device 228 to amplify the detected noise, and passes theamplified noise via Net 5 to the gate of NMOS device 220 using couplingcapacitor C2. NMOS device 220, in addition to receiving the noise at agate input, amplifies the detected noise further before outputting theamplified noise to the gate of PMOS power driver 208. This amplifiednoise is input to the gate of PMOS power driver 208 to change agate-source voltage of PMOS power driver 208 and to reduce the effectivepower supply voltage VDDQ noise reaching regulator output VREG. Theeffective bandwidth of third feedback loop 218 is higher than the powerdelivery network resonant frequency (e.g., at or about 150 MHz) in orderto minimize the impact of high frequency power supply voltage VDDQ noisereaching regulator output VREG. Third feedback loop 218 takes effectonce second feedback loop 216 no longer has an effect.

FIG. 3 illustrates a circuit-implemented method 300 for voltageregulation of a power supply signal. It will be appreciated that in acircuit implementing a method 300, the steps may occur simultaneouslyand continuously during circuit operation.

In a first step 302, a first feedback loop receives a reference voltageand a regulator output voltage. The first feedback loop may be firstfeedback loop 214 described in FIGS. 2A-2C, and the reference voltageand the regulator output voltage may include reference voltage VREF andregulated output voltage VREG.

In step 304, the first feedback loop detects low frequency noise of theregulator output. Step 304 may be achieved by reducing a DC voltageoffset between the reference voltage and the regulator output, whicheffectively outputs an output signal with a DC voltage value of thereference voltage and AC noise from the regulator output. In many cases,the first feedback loop is bandwidth-limited. As such, only the AC noiseat low frequencies are detected and included in the output signal. Thefirst feedback loop outputs the output signal as a low frequency noisesignal to a gate of a PMOS device of the first feedback loop, such asPMOS device 210 described in FIGS. 2A-2C.

In step 306, the first feedback loop, or other component of the circuit,applies the low frequency noise signal as negative feedback to theregulator output. For example, the low frequency noise signal isreceived as an input at the gate of the PMOS device of the firstfeedback loop, and applied as negative feedback to reduce differencesbetween the regulator output and the low frequency noise. The regulatoroutput is often less noisy than the low frequency noise signal due tothe regulated voltage being fed back through the circuit. As such, whenthe low frequency noise is applied as negative feedback to the regulatoroutput, the low frequency noise signal is used to filter out (e.g.,reduce) low frequency level noise on the regulator output as regulatoroutput traverses through the circuit, thereby resulting in alow-frequency filtered regulator output.

In step 308, bandwidth of the circuit implementing method 300 isincreased to enable detection of high frequency noise. Step 308 can beachieved by having a second feedback loop, such as second feedback loop216 described in FIG. 2B, having a comparatively higher bandwidth (e.g.,200 MHz bandwidth) than the first feedback loop (e.g., 20 MHzbandwidth), thereby increasing the overall bandwidth of the circuit. Thebandwidth of the circuit is increased a degree sufficient for the secondfeedback loop to filter (e.g., reduce) noise in a high frequency range.

In step 310, the second feedback loop, or other component of thecircuit, reduces high frequency noise of the low-frequency filteredregulator output generated in step 306. The second feedback loop appliesa high frequency negative feedback signal at a gate of an NMOS device ofthe circuit through which both the high frequency negative feedbacksignal and the low-frequency filtered regulator output pass, such asNMOS device 220 described in FIGS. 2A-2C. The negative feedback signalused to reduce the high frequency noise on the regulator output mayinclude a first DC bias voltage component generated from a noisy powersupply signal, where the value or amount of the first DC bias voltagecomponent is sufficient to reduce the high frequency noise in theregulator output at the NMOS device. As will be explained, a second DCbias voltage component is generated in another step and is used by theNMOS device to reduce very high frequency noise.

In step 312, a third feedback loop detects very high frequency noise ofthe regulator output, where the third feedback loop may be thirdfeedback loop 218 described in FIG. 2C. The components of the thirdfeedback loop capable of responding to noise at very high frequenciesabove the high frequencies, when components of the second feedback loopstop responding. The very high frequency noise is predominantly powersupply signal-induced noise, which can be confidently detected where thethird feedback loop has a configuration similar to that of a band-passcircuit and centered on a resonant frequency (e.g., 150 MHz to 170 MHz)of the power delivery network that is generating the power supplysignal. Step 312 may further include outputting a very high frequencynoise signal including the very high frequency noise.

In step 314, the third feedback loop applies the very high frequencynoise signal as negative feedback to reduce very high frequency noise onthe low-frequency filtered regulator output generated in step 306. Thisis achieved by outputting the very high frequency noise signal as asecond DC bias voltage component to the NMOS device, which effectivelyfilters the very high frequency noise out of the low-frequency filteredregulator output.

As steps 310 and 314 may be executed simultaneously ornear-simultaneously, the DC bias voltage on the gate of the NMOS devicecan have negative feedback components (e.g., first DC bias voltagecomponent, second DC bias voltage component) directed to reducing highfrequency noise and very high frequency noise. This enables the NMOSdevice, which the low-frequency filtered regulator output through, tofilter out (e.g., reduce) both high frequency and very high frequencynoise at the same time. Step 314 may further include outputting theregulator output as a regulated output voltage free of low, high andvery high frequency noise. In some embodiments, the step 314 may furtherinclude amplifying the very high frequency noise signal at an amplifierof the third feedback loop.

In step 316, the third feedback loop outputs the regulated outputvoltage from which low, high and very-high frequency noise has beenfiltered. In some cases, the regulator output is outputted as a filteredpower supply signal. The regulator output may be outputted to an inputof a comparator (e.g., comparator 202), a source of a PMOS device (e.g.,PMOS power driver 208), and to the third feedback loop. Method 300 mayend with step 316, or may cycle back to 302.

FIGS. 4A-4B illustrate effects of implementing circuit 200 and method300 within a system using a 24 Gbps GDDR6 PLL. FIG. 4A shows an exampleof PLL clock output deterministic accumulation jitter using an existingregulator architecture, such as that illustrated in FIG. 1B. Theaccumulation jitter measures at 5.38 ps. FIG. 4B shows an example of PLLclock output deterministic jitter using the proposed regulatorarchitecture of circuit 200. The accumulation jitter in this embodimentmeasures at 2.86 ps, showing that the proposed architecture reduces thedeterministic accumulation jitter of PLL due to power supply noise by50% with respect to the existing architecture.

With reference to FIGS. 2A-2C, the architecture of circuit 200 isdesigned such that feedback loops 214-218 work constantly to providenegative feedback to PMOS power driver 208 to reduce noise on theregulator output input to the PLL. FIGS. 4A-4B show that the solutioneffectively improves the PSR of the regulator output by 6 dB, which isequal to 50%, and reduces the 50 mV peak-to-peak noise of 167 MHz onpower supply voltage VDDQ to 2 mV peak-to-peak noise on regulator outputvoltage VREG. The improvement in the PSR contributes to reducingdeterministic accumulation jitter of 24 Gbps GDDR6 PLL by 50%, therebyensuring achievement of the deterministic accumulation jitter target forthe 24 Gbps GDDR6 PLL, and that the tight timing budget for the GDDR6interface is met. Furthermore, the addition of third feedback loop 218,geared towards very high frequency noise detection and correction forregulator output voltage VREG, provides significant improvement in highfrequency PSR with very small controlled bias current.

The various illustrative logical blocks, modules, circuits, andalgorithm steps described in connection with the embodiments disclosedherein may be implemented as electronic hardware, computer software, orcombinations of both. To clearly illustrate this interchangeability ofhardware and software, various illustrative components, blocks, modules,circuits, and steps have been described above generally in terms oftheir functionality. Whether such functionality is implemented ashardware or software depends upon the particular application and designconstraints imposed on the overall system. Skilled artisans mayimplement the described functionality in varying ways for eachparticular application, but such implementation decisions should not beinterpreted as causing a departure from the scope of the presentinvention.

Embodiments implemented in computer software may be implemented insoftware, firmware, middleware, microcode, hardware descriptionlanguages, or any combination thereof. A code segment ormachine-executable instructions may represent a procedure, a function, asubprogram, a program, a routine, a subroutine, a module, a softwarepackage, a class, or any combination of instructions, data structures,or program statements. A code segment may be coupled to another codesegment or a hardware circuit by passing and/or receiving information,data, arguments, parameters, or memory contents. Information, arguments,parameters, data, etc. may be passed, forwarded, or transmitted via anysuitable means including memory sharing, message passing, token passing,network transmission, etc.

The actual software code or specialized control hardware used toimplement these systems and methods is not limiting of the invention.Thus, the operation and behavior of the systems and methods weredescribed without reference to the specific software code beingunderstood that software and control hardware can be designed toimplement the systems and methods based on the description herein.

When implemented in software, the functions may be stored as one or moreinstructions or code on a non-transitory computer-readable orprocessor-readable storage medium. The steps of a method or algorithmdisclosed herein may be embodied in a processor-executable softwaremodule which may reside on a computer-readable or processor-readablestorage medium. A non-transitory computer-readable or processor-readablemedia includes both computer storage media and tangible storage mediathat facilitate transfer of a computer program from one place toanother. A non-transitory processor-readable storage media may be anyavailable media that may be accessed by a computer. By way of example,and not limitation, such non-transitory processor-readable media maycomprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage,magnetic disk storage or other magnetic storage devices, or any othertangible storage medium that may be used to store desired program codein the form of instructions or data structures and that may be accessedby a computer or processor. Disk and disc, as used herein, includecompact disc (CD), laser disc, optical disc, digital versatile disc(DVD), floppy disk, and Blu-Ray disc where disks usually reproduce datamagnetically, while discs reproduce data optically with lasers.Combinations of the above should also be included within the scope ofcomputer-readable media. Additionally, the operations of a method oralgorithm may reside as one or any combination or set of codes and/orinstructions on a non-transitory processor-readable medium and/orcomputer-readable medium, which may be incorporated into a computerprogram product.

The preceding description of the disclosed embodiments is provided toenable any person skilled in the art to make or use the presentinvention. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without departing from thespirit or scope of the invention. Thus, the present invention is notintended to be limited to the embodiments shown herein but is to beaccorded the widest scope consistent with the following claims and theprinciples and novel features disclosed herein.

While various aspects and embodiments have been disclosed, other aspectsand embodiments are contemplated. The various aspects and embodimentsdisclosed are for purposes of illustration and are not intended to belimiting, with the true scope and spirit being indicated by thefollowing claims.

What is claimed is:
 1. A voltage regulator circuit comprising: a firstfeedback circuit loop configured to: receive a reference voltage and avoltage regulator output; detect a low frequency noise from a regulatorpower supply on the voltage regulator output using the reference voltageand the voltage regulator output; and apply the low frequency noise as alow frequency negative feedback to the voltage regulator output, therebyreducing the low frequency noise on the voltage regulator output; asecond feedback circuit loop having a comparatively higher bandwidththan the first feedback circuit loop, and configured to: increasebandwidth of the voltage regulator circuit, and reduce a high frequencynoise originating from the regulator power supply by applying a biasvoltage comprising a portion of the regulator power supply as a highfrequency negative feedback; and a third feedback circuit loopconfigured to: detect a very high frequency noise from the regulatorpower supply on the voltage regulator output; apply the very highfrequency noise as a very high frequency negative feedback to thevoltage regulator output, thereby reducing the very high frequency noiseon the voltage regulator output; and output a regulated output equal tothe reference voltage and immune to the low frequency noise, the highfrequency noise, and the very high frequency noise from the regulatorpower supply.
 2. The voltage regulator circuit of claim 1, wherein thebandwidth of the first feedback circuit loop is less than 20 MHz and aDC gain of the first feedback circuit loop is greater than 40 dB.
 3. Thevoltage regulator circuit of claim 1, wherein the first feedback circuitloop is configured to apply the low frequency noise as the low frequencynegative feedback by inputting the low frequency noise to a gate of aPMOS device.
 4. The voltage regulator circuit of claim 1, wherein thebias voltage is an amount sufficient to reduce the high frequency noiseon the voltage regulator output.
 5. The voltage regulator circuit ofclaim 1, wherein the bandwidth of the second feedback circuit loop is200 MHz.
 6. The voltage regulator circuit of claim 1, wherein the thirdfeedback circuit loop, when applying the very high frequency noise asthe very high frequency negative feedback, is configured to: amplify thevery high frequency noise, thereby producing amplified very highfrequency noise; receive the amplified very high frequency noise as thevery high frequency negative feedback at a gate of an NMOS device;receive a fraction of the voltage regulator output at a source of theNMOS device; and reduce the very high frequency noise on the voltageregulator output.
 7. The voltage regulator circuit of claim 1, whereinthe very high frequency noise detected by the third feedback circuitloop is within a predetermined threshold of a power delivery networkresonant frequency.
 8. The voltage regulator circuit of claim 7, whereinthe third feedback circuit loop is a band-pass filter with a bandfrequency centered on the power delivery network resonant frequency. 9.The voltage regulator circuit of claim 7, wherein the bandwidth of thethird feedback circuit loop is greater than the power delivery networkresonant frequency.
 10. The voltage regulator circuit of claim 7,wherein the power delivery network resonant frequency is at or about 150MHz.
 11. A method for voltage regulation in a circuit, the methodcomprising: receiving, by a first feedback circuit loop, a referencevoltage and a voltage regulator output; detecting, by the first feedbackcircuit loop, a low frequency noise from a regulator power supply on thevoltage regulator output using the reference voltage and the voltageregulator output; applying, by the first feedback circuit loop, the lowfrequency noise as negative feedback to the voltage regulator output,thereby reducing the low frequency noise on the voltage regulatoroutput; increasing, by a second feedback circuit loop, bandwidth of thecircuit, the second feedback circuit loop having a comparatively higherbandwidth than the first feedback circuit loop, reducing, by the secondfeedback circuit loop, high frequency noise on the voltage regulatoroutput by applying a bias voltage comprising a portion of the regulatorpower supply as a high frequency negative feedback; detecting, by athird feedback circuit loop, very high frequency noise from theregulator power supply on the voltage regulator output; applying, by thethird feedback circuit loop, the very high frequency noise as negativefeedback to the voltage regulator output, thereby reducing the very highfrequency noise on the voltage regulator output; and outputting, by thethird feedback circuit loop, a regulated output equal to the referencevoltage and immune to the low frequency noise, the high frequency noise,and the very high frequency noise from the regulator power supply. 12.The method for voltage regulation of claim 11, wherein the bandwidth ofthe first feedback circuit loop is less than 20 MHz and DC gain of thefirst feedback circuit loop is greater than 40 dB.
 13. The method forvoltage regulation of claim 11, wherein applying the low frequency noiseas negative feedback comprises inputting the low frequency noise to agate of a PMOS device.
 14. The method for voltage regulation of claim11, wherein the bias voltage is an amount sufficient to reduce the highfrequency noise on the voltage regulator output.
 15. The method forvoltage regulation of claim 11, further wherein the bandwidth of thesecond feedback circuit loop is 200 MHz.
 16. The method for voltageregulation of claim 11, wherein applying the very high frequency noiseas very high frequency negative feedback by the third feedback circuitloop further comprises: amplifying the very high frequency noise,thereby producing amplified very high frequency noise; receiving, at agate of an NMOS device, the amplified very high frequency noise asnegative feedback; receiving, at a source of the NMOS device, a fractionof the voltage regulator output; and reducing the very high frequencynoise of the voltage regulator output.
 17. The method for voltageregulation of claim 11, wherein the very high frequency noise detectedis within a predetermined threshold of a power delivery network resonantfrequency.
 18. The method for voltage regulation of claim 17, whereinthe third feedback circuit loop is a band-pass filter with a bandfrequency centered on the power delivery network resonant frequency. 19.The method for voltage regulation of claim 17, wherein the bandwidth ofthe third feedback circuit loop is greater than the power deliverynetwork resonant frequency.
 20. The method for voltage regulation ofclaim 17, wherein the power delivery network resonant frequency is at orabout 150 MHz.